Computer Architecture |
Course
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Due Monday, April 30, by class time - MML4: Completed CPU with sample program illustrating indirect addressing. Be sure to provide a documented program listing (pseudocode)
Due Monday, April 16: Turn in written solutions (with explanations) for questions 16, 20 (explain why 4 bytes is not feasible), 24 (pages 327-329) and one additional problem: Create a table like 4-33 to illustrate the pipelined microcode for MIC-3 for the istore instruction (see page 282 for the microcode). Comment on the speed increase.
Due Monday, April 9, by class time - MML3: CPU part II (scroll down to the new section of the assignment) (Get revised clock module)
Due Friday, March 30 : Turn in written solutions (with explanations) for questions 1-6, 8, 11, 13, 15 (pages 327-329). There is a misprint in 13a: the phrase 'left right' should be 'shifting right'
Due Wednesday, March 14, MML2: CPU part I
Due Monday, March 5, PG1 Assessment: Answer the following questions about the Decitak programming project.
Due Monday, Feb 26, HW4: Ch 3b Assignment: Turn in written solutions for problems 18, 20, 23 (pages 226-230). Implement a 4-bit register using edge-triggered data latches, which, together with your ALU, will simulate a simple program counter and instruction fetch unit. A clock signal (running at 1 HZ) will cause the PC to increment by 1 on each clock pulse and fetch an instruction from ROM. The instruction is displayed on an ASCII Display unit. Place the register logic on one page. Use signal receivers for a CLR_PC signal and 4 data input lines (PCIN_0 through PCIN_3. We also need a clock (CLK) and an enable line (PC_EN) that prevents the clock signal from causing changes to PC unless it is enabled. Of course, PCOUT_0 through 3 should be signal senders. On a separate page, provide a pushbutton to clear the PC and a toggle switch to enable it. Place a clock, memory, and ASCII display on this page. Connect up the register using signal senders/receivers. The PC should address memory (addresses 0-F only). Memory data is read only and sent directly to an ASCII display unit. Preset memory to contain your first and last name (separated by a CR). Pad with a few spaces, and then add null characters to complete the first 16 bytes of memory. Each character will be an instruction of a ML program that you will be executing. The computer actually just displays the instructions as the execute step! The null character is a special instruction. It will cause a reset of PC and a clear of the display. Include a visual display of the PC value on your main page.
Due Friday, Feb 16, MML1: Implement a 4-bit ALU. Use Multimedia Logic to design and test a 4-bit ALU. The ALU allows 2 4 bit inputs (A and B) to be added or subtracted. The A and B inputs have enable lines. There is a SUBtract control line named SUB, and 4 outputs (C) plus a ZERO output (logic 1 when the result is 0). You will need the following input connections (signal receivers) on the circuit. A0-A3, B0-B3, ENA, ENB, and SUB. The following output connections (signal senders) are also required. C0-C3 and ZERO. Create a test curcuit on a separate page that uses two BCD switches for A and B, toggle switches for ENA, ENB, and SUB, and a 7-segment display for the output. The decimal point can be used for the ZERO output of the ALU. Be sure that your ALU adds when SUB is 0, and subtracts when SUB is 1. How can the ALU be used to increment a 4 bit value (regardless of the second input)? Use the Text tool to provide your name, labels, and brief instructions on your circuit. You should submit the resulting logic file to me via email.
Due Wednesday, Feb 14, HW3: Ch 3a Assignment: Turn in written solutions for problems 1, 3, 6, 8, 11 (Find an equivalent circuit in the book!), 15, 17 (pages 226-230)
Due Friday, Feb 9, HW2: Ch 2 Assignment: Turn in written solutions (with explanations) for questions 1, 3, 6, 8, 12, 29 (pages 132-134).
Due by the end of the day, Tuesday, February 20: Decitak programming project (see the forum link on the main page)
Due Monday, Jan 22: HW1: Pick one historical computer (pre 1980) or one individual responsible for an historical hardware or software innovation and write a 300-500 word report about the computer or individual and innovation. Provide references using the ACM style guide. You can look here for style information. Submit as a Word document (named lastname_HW1.doc but substitute your last name please) via email attachment (margush@cs.uakron.edu) with subject line Architecture HW1.